Overlapping Clocks Defined on the Same Clock Source - 2021.2 English

UltraFast Design Methodology Guide for Xilinx FPGAs and SoCs

Document ID
UG949
Release Date
2021-11-19
Version
2021.2 English

This occurs when two clocks are defined on the same netlist object with the create_clock -add command and represent the multiple modes of an application. In this case, it is safe to apply a clock groups constraint between the clocks. For example:

create_clock -name clk_mode0 -period 10 [get_ports clkin]
create_clock -name clk_mode1 -period 13.334 -add [get_ports clkin]
set_clock_groups -physically_exclusive -group clk_mode0 -group clk_mode1

If the clk_mode0 and clk_mode1 clocks generate other clocks, the same constraint needs to be applied to their generated clocks as well, which can be done as follows:

set_clock_groups -physically_exclusive \
-group [get_clocks -include_generated_clock clk_mode0] \
-group [get_clocks -include_generated_clock clk_mode1]