Power Timing Slack - 2021.2 English

UltraFast Design Methodology Guide for Xilinx FPGAs and SoCs

Document ID
UG949
Release Date
2021-11-19
Version
2021.2 English

When closing a design for timing, it is more efficient and effective to simultaneously close the design from a power perspective. This approach allows for the best run selection that satisfies both criteria. To close both timing and power, add the report_power constraint to the script you are running. For more information and an example script, see Xilinx Answer Record 76056.

The following figure shows an example of this approach. For all 64 timing closure runs, report power was also run, and all runs are plotted together. From the graph, 36 runs were timing clean, and from a power perspective, the total power budget is 77W. The 64 runs were in the range of 75W to 83W, an 8W or ~10% range.

Looking at the best run from a timing perspective, run #6 had a power estimate of 79.5W, which exceeds the total power budget. However, from the timing clean runs, run #13 yielded the lowest power at 75W and was still timing clean. Understanding the design from both a timing and power perspective allows you to select the best run for both, without impacting the timing result. In this example, this approach enabled a 4W power saving.

Power Tip: You can also improve design power by removing the DONT_TOUCH constraint to allow upfront logic trimming, including clocking primitives.
Figure 1. Power and Timing Slack for Different Place and Route Runs