Reset Coding Example: Multiplier with Asynchronous Reset - 2021.2 English

UltraFast Design Methodology Guide for Xilinx FPGAs and SoCs

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2021.2 English

The following example illustrates the importance of using registers with synchronous resets for the logic targeting the dedicated DSP resources. The following figure shows a 16x16 bits DSP48-based multiplier using pipeline registers with asynchronous reset. Synthesis must use regular fabric registers for the input stages, as well as an external register and 32 LUT2s (red markers) to emulate the asynchronous reset on the DSP output (DSP48 P registers are enabled but not connected to reset). This costs an extra 65 registers and 32 LUTs, and the DSP48 results in the configuration: AREG/BREG=0, MREG=0, PREG=1.

Figure 1. Multiplier with Pipeline Registers Using Asynchronous Resets

By simply changing the reset definition as shown in the following figure, such that the multiplier pipeline registers use a synchronous reset, synthesis can take advantage of the DSP48 internal registers: AREG/BREG=1, MREG=1, PREG=1.

Figure 2. Changing Asynchronous Reset into Synchronous Reset on Multiplier

Due to saving fabric resources and taking advantage of all DSP48 internal registers, the design performance and power efficiency are optimal.