Super Long Line (SLL) Routes - 2021.2 English

UltraFast Design Methodology Guide for Xilinx FPGAs and SoCs

Document ID
UG949
Release Date
2021-11-19
Version
2021.2 English

Super Long Line (SLL) routes connect signals from one SLR to another inside the device.

Tip: To determine the number of available SLLs between SLRs, use SLR properties. For example:
get_property NUM_TOP_SLLS [get_slrs SLR0]
get_property NUM_BOT_SLLS [get_slrs SLR1]