Synchronous - 2021.2 English

UltraFast Design Methodology Guide for Xilinx FPGAs and SoCs

Document ID
UG949
Release Date
2021-11-19
Version
2021.2 English

Clock relationships are synchronous when two clocks have a fixed phase relationship. This is the case when two clocks share the following:

  • Common circuitry (common node)
  • Primary clock (same initial phase)