Using Clock Modifying Blocks (MMCM and PLL) - 2021.2 English

UltraFast Design Methodology Guide for Xilinx FPGAs and SoCs

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2021.2 English

You can use an MMCM or PLL to change the overall characteristics of an incoming clock. An MMCM is most commonly used to remove the insertion delay of the clock (phase align the clock to the incoming system synchronous data) or for conditioning and controlling the clock characteristics, such as:

  • Creating tighter control of phase
  • Filtering jitter in the clock
  • Changing the clock frequency
  • Correcting or changing the clock duty cycle

To use the MMCM or PLL, several attributes must be coordinated to ensure that the MMCM is operating within specifications and delivering the desired clocking characteristics on its output. For this reason, Xilinx highly recommends that you use the Clocking Wizard to properly configure this resource.

You can also directly instantiate the MMCM or PLL, which allows even greater control. However, be sure to use the proper settings to avoid causing the following issues:

  • Increasing clock uncertainty due to increased jitter
  • Building incorrect phase relationships
  • Making timing closure more difficult
    Important: When using the Clocking Wizard to configure the MMCM or PLL, the Clocking Wizard by default attempts to configure the MMCM for low output jitter using reasonable power characteristics.

Depending on your goals, you can change the settings in the Clocking Wizard to further minimize jitter and thus, improve timing at the cost of higher power. Alternatively, you can reduce power but increase output jitter.

While using MMCM or PLL, be sure to do the following:

  • Do not leave any inputs floating. Relying on synthesis or other optimization tools to tie off the floating values is not recommended, because the values might be different than expected.
  • Connect RST to the user logic, so that it can be asserted by logic controlled by a reliable clocking source. Grounding of RST can cause problems if the clock is interrupted.
  • Use LOCKED output in the implementation of reset. For example, hold the synchronous logic clocked from the PLL in reset until LOCKED is asserted. The LOCKED signal must be synchronized before it is used in a synchronous portion of the design. Xilinx recommends adding LOCKED to a processor map so it is visible when debugging.
  • Confirm the connectivity between CLKFBIN and CLKFBOUT. The BUFG only needs to be included in the feedback path if the PLL/MMCM output clock needs to be phase aligned with the input reference clock, for example, when using ZHOLD compensation mode.
  • To avoid the MMCM or PLL phase error timing penalty on synchronous clock domain crossing paths in UltraScale devices, use BUFGCE_DIVs instead of BUFGCE.