The In-System IBERT core provides RX margin analysis through eye scan plots on
the RX data of transceivers in UltraScale and
UltraScale+ devices. The core enables
configuration and tuning of the GTH/GTY transceivers and is accessible through logic
that communicates with the dynamic reconfiguration port (DRP) of the transceivers. You
can use the core to change attribute settings as well as registers that control the
values on the
The Vivado Serial I/O Analyzer in the Hardware Manager communicates with the core through JTAG when the design is programmed onto the device. There is only one instance of In-System IBERT required per design. In-System IBERT can work with all GTs used in the design. However, you must generate separate In-System IBERT cores according to the different GT types (for example, GTH, GTY).
Creating an In-System IBERT design with an internal system clock can prevent a
scan from being performed. When creating an eye scan, the status changes from In Progress to Incomplete. Eye scan is incomplete when the internal system clock
(MGTREFCLK) is connected to the
port of In-System IBERT IP.
For more information on this core, see the In-System IBERT LogiCORE IP Product Guide (PG246).