To automatically address most timing closure challenges during
implementation, you can use an Intelligent Design Run (IDR). An IDR is a special type of
implementation run that leverages
report_qor_suggestions, ML-based strategy predictions, and incremental
compile. An IDR can run up to 6 iterations of place and route, which leads to a typical
compile time of 4.5 times that of a standard run. However, using IDR can provide
significant benefits by reducing the knowledge required to close timing and by saving
hours of user analysis.
report_qor_suggestionsto apply optimization properties to elements in the design in a predetermined order.
- Uses machine learning (ML) strategies to generate tool options
route_designthat are optimized for the design.
- Uses a Last Mile Timing Closure feature to apply extensive effort on paths that are difficult to resolve to get the final result.
To ensure success when using IDR, follow these requirements:
- The implementation must be project based. For non-project users, the
easiest method is to create a post-synthesis netlist-based project using a
- The device must be from either an UltraScale or UltraScale+™ - device-based family.
- The design must have a baseline with accurate and achievable constraints.
- All designs must comply with the recommended methodology, as
reported by the
- An SLR-based floorplan might be required for SSI technology-based devices.
- Apply only automatic implementation suggestions. Text-based
suggestions or suggestions with
APPLICABLE_FOR = synth_designmust be applied before starting an IDR.
For more information see this link in the Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906).