Primitive: Local Clock Buffer for I/O
This design element is a local clock-in, clock-out buffer. It drives a dedicated clock net within the I/O column, independent of the global clock resources and is ideally suited for source-synchronous data capture (forwarded/receiver clock distribution). BUFIO elements can be driven by a dedicated MRCC I/O located in the same clock region, or a BUFMRCE/BUFMR component capable of clocking multiple clock regions. BUFIO can only drive I/O components within the bank in which they exist. They cannot directly drive logic resources (CLB, block RAM, etc.) because the I/O clock network only reaches the I/O column.
|I||Input||1||Input port to clock buffer. Connect this to an IBUF connected to a top-level port or an associated BUFMR buffer.|
|O||Output||1||Output port from clock buffer. Connect this to the clock inputs to synchronous I/O components like the ISERDESE2, OSERDESE2, IDDR, ODDR or register connected directly to an I/O port (inferred or instantiated).|
Design Entry Method
VHDL Instantiation Template
Library UNISIM; use UNISIM.vcomponents.all;
-- BUFIO: Local Clock Buffer for I/O -- 7 Series -- Xilinx HDL Language Template, version 2021.2 BUFIO_inst : BUFIO port map ( O => O, -- 1-bit output: Clock output (connect to I/O clock loads). I => I -- 1-bit input: Clock input (connect to an IBUF or BUFMR). ); -- End of BUFIO_inst instantiation
Verilog Instantiation Template
// BUFIO: Local Clock Buffer for I/O // 7 Series // Xilinx HDL Language Template, version 2021.2 BUFIO BUFIO_inst ( .O(O), // 1-bit output: Clock output (connect to I/O clock loads). .I(I) // 1-bit input: Clock input (connect to an IBUF or BUFMR). ); // End of BUFIO_inst instantiation
- See the 7 Series FPGAs Clocking Resource User Guide (UG472).