Primitive: Input Double Data-Rate Register with Dual Clock Inputs
This design element is a dedicated input register designed to receive external double data rate (DDR) signals into Xilinx® FPGAs. You should only use the IDDR_2CLK for very high speed interfaces, because it requires more clocking resources, more power, and can imply certain placement restrictions that are not necessary when using the IDDR component. The IDDR component is also easier to use, uses fewer resources, and has fewer restrictions, though it cannot operate at the same high I/O speeds. The IDDR_2CLK is available with modes that present the data to the FPGA fabric at the time and clock edge they are captured, or on the same clock edge. This feature allows designers to avoid additional timing complexities and resource usage.
OPPOSITE_EDGE mode: Data is presented in the classic DDR methodology. Given a DDR data and clock at pin D and C respectively, Q1 changes after every positive edge of clock C, and Q2 changes after every positive edge of clock CB.
SAME_EDGE mode: Data is still presented by positive edges of each clock. However, an extra register has been placed in front of the CB clocked data register. This extra register is clocked with positive clock edge of clock signal C. As a result, DDR data is now presented into the FPGA fabric at the positive edge of clock C. However, because of this feature, the data pair appears to be "separated." Q1 and Q2 no longer have pair 1 and 2. Instead, the first pair presented is Pair 1 and DON'T CARE, followed by Pair 2 and 3 at the next clock cycle.
SAME_EDGE_PIPELINED mode: Presents data in a similar fashion as the SAME_EDGE mode. In order to avoid the "separated" effect of the SAME_EDGE mode, an extra register has been placed in front of the C clocked data register. A data pair now appears at the Q1 and Q2 pin at the same time during the positive edge of C. However, using this mode requires an additional cycle of latency for Q1 and Q2 signals to change.
IDDR also works with SelectIO™ features, such as the IODELAYE2.
|Q1 : Q2||Output||1||These pins are the IDDR output that connects to the FPGA fabric. Q1 is the first data output and Q2 is the second data output.|
|C||Input||1||Primary clock input pin used to capture the positive edge data.|
|CB||Input||1||Secondary clock input pin (typically 180 degrees out of phase with the primary clock) used to capture the negative edge data.|
|CE||Input||1||When asserted Low, this port disables the output clock at port O.|
|D||Input||1||This pin is where the DDR data is presented into the IDDR module. It connects to a top-level input or bi-directional port, and IODELAY configured for an input delay or to an appropriate input or bidirectional buffer.|
|R||Input||1||Active-High reset forcing Q1 and Q2 to a logic one. Can be synchronous or asynchronous based on the SRTYPE attribute.|
|S||Input||1||Active-High reset forcing Q1 and Q2 to a logic zero. Can be synchronous or asynchronous based on the SRTYPE attribute.|
Design Entry Method
Connect the C pin to the appropriate clock source, representing the positive clock edge and CB to the clock source representing the negative clock edge.
Connect the D pin to the top-level input, or bidirectional port, an IODELAY, or an instantiated input or bidirectional buffer.
The Q1 and Q2 pins should be connected to the appropriate data sources.
CE should be tied high when not used, or connected to the appropriate clock enable logic.
R and S pins should be tied low, if not used, or to the appropriate set or reset generation logic.
Set all attributes to the component to represent the desired behavior.
Always instantiate this component in pairs with the same clocking, and to LOC those to the appropriate P and N I/O pair in order not to sacrifice possible I/O resources.
Always instantiate this component in the top-level hierarchy of your design, along with any other instantiated I/O components for the design. This helps facilitate hierarchical design flows/practices.
To minimize CLK skew, both CLK and CLKB should come from global routing (MMCM) and not from the local inversion. MMCM de-skews these clocks whereas the local inversion adds skew.
|DDR_CLK_EDGE||STRING||"OPPOSITE_EDGE","SAME_EDGE""SAME_EDGE_PIPELINED"||"OPPOSITE_EDGE"||DDR clock mode recovery mode selection. See Introduction for more explanation.|
|INIT_Q1||BINARY||0, 1||0||Initial value on the Q1 pin after configuration startup or when GSR is asserted.|
|INIT_Q2||BINARY||0, 1||0||Initial value on the Q2 pin after configuration startup or when GSR is asserted.|
|SRTYPE||STRING||"SYNC" or "ASYNC"||"SYNC"||Set/reset type selection. SYNC" specifies the behavior of the reset (R) and set (S) pins to be synchronous to the positive edge of the C clock pin. "ASYNC" specifies an asynchronous set/reset function.|
VHDL Instantiation Template
Library UNISIM; use UNISIM.vcomponents.all;
-- IDDR_2CLK: Dual-Clock, Input Double Data Rate Input Register with -- Set, Reset and Clock Enable. -- 7 Series -- Xilinx HDL Language Template, version 2021.2 IDDR_2CLK_inst : IDDR_2CLK generic map ( DDR_CLK_EDGE => "OPPOSITE_EDGE", -- "OPPOSITE_EDGE", "SAME_EDGE" -- or "SAME_EDGE_PIPELINED" INIT_Q1 => '0', -- Initial value of Q1: '0' or '1' INIT_Q2 => '0', -- Initial value of Q2: '0' or '1' SRTYPE => "SYNC") -- Set/Reset type: "SYNC" or "ASYNC" port map ( Q1 => Q1, -- 1-bit output for positive edge of clock Q2 => Q2, -- 1-bit output for negative edge of clock C => C, -- 1-bit primary clock input CB => CB, -- 1-bit secondary clock input CE => CE, -- 1-bit clock enable input D => D, -- 1-bit DDR data input R => R, -- 1-bit reset S => S -- 1-bit set ); -- End of IDDR_2CLK_inst instantiation
Verilog Instantiation Template
// IDDR_2CLK: Dual-Clock, Input Double Data Rate Input Register with // Set, Reset and Clock Enable. // 7 Series // Xilinx HDL Language Template, version 2021.2 IDDR_2CLK #( .DDR_CLK_EDGE("OPPOSITE_EDGE"), // "OPPOSITE_EDGE", "SAME_EDGE" // or "SAME_EDGE_PIPELINED" .INIT_Q1(1'b0), // Initial value of Q1: 1'b0 or 1'b1 .INIT_Q2(1'b0), // Initial value of Q2: 1'b0 or 1'b1 .SRTYPE("SYNC") // Set/Reset type: "SYNC" or "ASYNC" ) IDDR_2CLK_inst ( .Q1(Q1), // 1-bit output for positive edge of clock .Q2(Q2), // 1-bit output for negative edge of clock .C(C), // 1-bit primary clock input .CB(CB), // 1-bit secondary clock input .CE(CE), // 1-bit clock enable input .D(D), // 1-bit DDR data input .R(R), // 1-bit reset .S(S) // 1-bit set ); // End of IDDR_2CLK_inst instantiation
- See the 7 Series FPGA SelectIO Resources User Guide (UG471).