Vivado Design Suite User Guide: Designing IP Subsystems Using IP Integrator - 2021.2 English

Document ID: UG994
Release Date: 2021-10-27
Version: 2021.2 English

Revision History
Getting Started with Vivado IP Integrator
Navigating Content by Design Process
Creating a Block Design
Creating a Project
Creating a Block Design
Designing with IP Integrator
Adding IP Modules to the Design Canvas
Adding RTL Modules to the Block Design
Making Connections
Connecting Interface Signals
External Connections
Making Ports External
Creating Ports
Creating Interface Ports
Handling Interrupts
Using the Designer Assistance Feature
Using the Signals View to Make Connections
Using Make Connections to Connect Ports and Pins
Making Connections with Start Connection Mode
Interfacing with AXI IP Outside of the Block Design
Re-Arranging the Design Canvas
Creating Hierarchies
Adding Pins and Interfaces to Hierarchies
Cutting and Pasting
Adding Comments to Block Designs
Pinning Blocks and Ports to Location
Using Mouse Strokes and the Toolbar Buttons
Displaying Layers in the Block Design
Defining Colors in the Block Design
Controlling Views Using the General Tab
Working with Presets to Control Block Design Views
Hierarchical IP in IP Integrator
InterConnect vs. SmartConnect
Glue Logic IP in IP Integrator
Utility Vector Logic
Utility Reduced Logic
Constant
Utility Buffer
Concat
Slice
About On-Disk Objects and In-Memory Objects
Block Designs
IP Instances or Block Design Cells
Validating a Block Design
Generating/Resetting Output Products
Running Design Rule Checks
Connecting Ports with Different Widths
Finding Objects in a Block Design
Addressing for Block Designs
Addressing Overview
Addressing Structure
Concepts
Using the Address Editor
Editor Rows
Editor View Groups
Editor Columns
Editing Addresses
Assigning Multiple Address Ranges for External Segments
Importing and Exporting Address Map from the Address Editor
Address Path Property View
Apertures
Cross Probing with Address Editor
Address Map
Address Map Structure
Slaves
Masters
Working with the Address Map
Scale and Zoom
Show in Browser
Block Diagram Addressing View
Common Addressing-Related Critical Warnings and Errors
Working with Block Designs
Generating Output Products
Using the Generate Output Products Dialog Box
Examining Generated Output Products
Integrating the Block Design into a Top-Level Design
Instantiating I/O Buffers
Adding Existing Block Designs
Adding Read-Only Block Designs
Adding and Associating an ELF File to an Embedded Design
Adding ELF and Associating it With an Embedded Processor
Saving a Block Design with a New Name
Comparing Two Block Designs
Navigating in the HTML Diff Report
Cross-Probing Differences in the Block Designs
diffbd Command Line Utility
Packaging a Block Design
Collaborative Design in IP Integrator
Modular Design with Block Design Containers
Introduction to Block Design Containers
Creating Block Design Containers
Top Down Design Flow
Bottom Up Design Flow
Working with Block Design Containers
Viewing the Content of Block Design Containers Within Top-Level BD
Applying Changes to Block Design Containers
Syncing Changes Between BDCs and Top-Level BD
Addressing of BDCs Within Top-Level BD
Configuring Block Design Containers from Top BD
Parameter Propagation of Block Design Containers from Top BD
Design Re-Use with Block Design Containers
Single vs Multiple Project(s)
Replication of Sub-Blocks within a BD
Revision Control for Block Designs
IP and IP Integrator Directory Structure
Revision Control Methodology
Cross-Probing Timing Paths
Propagating Parameters in IP Integrator
Using Bus Interfaces
Common Internal Bus Interfaces
Parameter Propagation
Parameters in the Customization GUI
Debugging IP Integrator Designs
Using the HDL Instantiation Flow in IP Integrator
Using the System ILA IP to Debug a Block Design
Manually Configuring the System ILA
Validating the System ILA
Using the ILA IP to Debug a Block Design
Creating a Block Design to Use the Board Flow
Using the Netlist Insertion Flow
Marking Nets for Debug in the Block Design
Generating Output Products
Synthesize the Design and Insert the ILA Core
Removing Debug Logic after Debug
Parameter Mismatch Example
Using Tcl Scripts to Create Projects and Block Designs
Exporting a Block Design to a Tcl Script in the IDE
Saving Vivado Project Information in a Tcl File
Using IP Integrator in Non-Project Mode
Creating a Flow in Non-Project Mode
Non-Project Script
Updating Designs for a New Release
Upgrading a Block Design in Project Mode
Regenerating Output Products
Upgrading a Block Design in Non-Project Mode
Selectively Upgrading IP in Block Designs
Requirements of Selectively Upgrading IP in Block Designs
Selectively Upgrading IP Flow in Project Mode
Limitations of Selectively Upgrading IP in Block Designs
Using the Platform Board Flow in IP Integrator
Selecting a Target Board
Downloading Third-Party Board Files from GitHub Using the GUI
Creating a Block Design to Use the Board Flow
Completing Connections in the Block Design
Archiving a Project When Board Flow is Used
Using Third-Party Synthesis Tools in IP Integrator
Setting the Block Design as Out-of-Context Module
Creating an HDL or EDIF Netlist in Synplify
Creating a Post-Synthesis Project in Vivado
Adding Top-Level Constraints
Adding an ELF File
Implementing the Design
Referencing RTL Modules
Referencing a Module
XCI Inferencing
IP and Reference Module Differences
Inferring Generics/Parameters in an RTL Module
Inferring Control Signals in a RTL Module
Inferring AXI Interfaces
Prioritizing Interfaces for Automatic Inference
HDL Parameters for Interface Inference
General Usage
List of Supported X_ Attributes
Editing the RTL Module After Instantiation
Module Reference in a Non-Project Flow
Reusing a Block Design Containing a Module Reference
Handling Constraints in RTL Modules
Limitations of the Module Reference Feature
Creating Vitis Platforms Using Vivado/IP Integrator
Creating the Platform Project in Vivado
Setting Up Platform (PFM) Interfaces and Properties
Working with Platform Setup Window
Interface Type Settings
Exporting Platforms to Vitis
Supported Project Structures to Export to Vitis
Additional Resources and Legal Notices
Xilinx Resources
Solution Centers
Documentation Navigator and Design Hubs
References
Training Resources
Please Read: Important Legal Notices

Back to home page