You can create entire designs using IP integrator; however, the typical design consists of HDL, IP, and IP integrator block designs (BDs). This section is an introduction to creating a new IP integrator-based design.
To create a project, click Create Project in the Vivado® IDE graphical user interface (GUI), as shown in the following figure.
To add or create a BD in a project, create an RTL project, or select Example Project. You can add HDL design files, user constraints, and other types of design source files to the project using the New Project wizard.
After adding design sources, existing IP, and design constraints, you can also select the default Xilinx® device or platform board to target for the project, as shown in the following figure. For more information, see Using the Platform Board Flow in IP Integrator.
create_project <project_name> <project_path> -part <part> set_property BOARD_PART <board_part> [current_project] set_property TARGET_LANGUAGE <vhdl/verilog> [current_project]
See the Vivado Design Suite Tcl Command Reference Guide (UG835) for information on specific Tcl commands.