Cross-Probing Timing Paths - 2021.2 English

Vivado Design Suite User Guide: Designing IP Subsystems Using IP Integrator

Document ID
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2021.2 English
Often times there is a need to probe a timing issue after implementation, to a source block in IP Integrator design. This can be useful when a user is not intimately aware of a design inherited from another team member. To isolate a timing path to a particular block, the user can open up the implemented design and click on the link to point to the source block of the timing issue in question on the block design canvas. As an example, in the following implemented design, there is a methodology warning on an IP block.
Figure 1. Methodology Warning
The message here says:
CLKC #1 The MMCME3 cell config_mb_i/axi_ethernet_0/inst/pcs_pma/inst/core_clocking_i/mmcme3_adv_inst has COMPENSATION value ZHOLD, but CLKOUT2 output drives sequential IO cells. In order to achieve insertion delay and phase-alignment for the IO sequential cells, CLKOUT0 must be used. 

As you can see in the message the path cell config_mb_i/axi_ethernet_0/inst/pcs_pma/inst/core_clocking_i/mmcme3_adv_inst has a link. Clicking this link will take you to the block design canvas and highlight the block design cell related to this timing message.

To see the cell in question on the block design canvas, click IP INTEGRATOR in Flow Navigator to switch view to the Block Design Canvas.
Figure 2. Highlighted Cell in the Message on the Block Design Canvas

Once the offending cell or IP block has been identified, the user can then look at the source code or the constraints file to identify the issue in hand.