As FPGAs become larger and more complex, and as design schedules become shorter, use of third-party IP and design reuse is becoming mandatory. Xilinx® recognizes the challenges designers face, and to aid designers with design and reuse issues, has created a powerful feature within the Vivado® Design Suite called the Vivado IP integrator.
The Vivado IP integrator lets you create complex system designs by instantiating and interconnecting IP from the Vivado IP catalog on a design canvas. You can create designs interactively through the IP integrator canvas GUI or programmatically through a Tcl programming interface. Designs are typically constructed at the interface level (for enhanced productivity) but may also be manipulated at the port level (for precision design manipulation).
An interface is a grouping of signals that share a common function. An AXI4-Lite master, for example, contains a large number of individual signals plus multiple buses, which are all required to make a connection. If each signal or bus is visible individually on an IP symbol, the symbol is visually very complex. By grouping these signals and buses into an interface, the following advantages can be realized:
- A single connection in IP integrator (or Tcl command) creates a master to slave connection.
- The graphical representation of this connection is a simple, single connection.
- Design Rule Checks (DRCs) that are aware of the specific interface can be run to assure that all the required signals are connected properly.
A key strength of IP integrator is that it provides a Tcl command language extension mechanism for its automation services so that system design tasks, such as parameter propagation, can be optimized per-IP or application domain.
Additionally, IP integrator implements dynamic, run-time DRCs to ensure that connections between the IP in an IP integrator design are compatible and that the IP themselves are properly configured.