The following limitations exist in the Module Reference feature:
- Because a module reference is not an IP, you cannot specify the Vendor, Library, Name, and Version (VLNV).
- The RTL module definition cannot include netlists (EDIF or DCP), nested block designs (BD) or another module that is set as out-of-context (OOC) inside the RTL module.
- VHDL and Verilog are the only supported languages for module definition. A block design containing a module reference cannot be packaged as an IP. Instead, package the module as an IP separately, and then package the BD including that IP.
- Module Reference blocks cannot be opted out of upgrade while migrating a design from a previous version of Vivado.
- IP caching is not supported for Module Reference blocks.
Tip: SystemVerilog and VHDL 2008 are not supported for the module or entity definition at the top-level of the RTL module.