IP integrator offers a feature called Designer Assistance, which includes Block Automation and Connection Automation, to assist you in putting together a basic IP sub-system by making internal connections between different blocks and making connections to external interfaces. The Block Automation Feature is provided when an embedded processor such as the Zynq-7000 Processor System 7 (ZYNQPS7), a Zynq MPSoC (Zynq_ultra_ps_e_0), a MicroBlaze processor, or some other hierarchical IP such as an Ethernet is instantiated in the IP integrator BD.
Using Block Automation
Designer assistance can help you put together a simple MicroBlaze system. To use this feature:
- Click the Run Block Automation link in the
banner of the design canvas, as shown in the following figure.
The Run Block Automation dialog box opens, as shown in the following figure.
- Provide input about basic features that the microprocessor
After you specify the necessary options, the Block Automation feature automatically creates a basic system, as shown in the following figure.
For example, the MicroBlaze System shown in the following figure consists of the following:
- A MicroBlaze Debug Module
- A hierarchical block called the
microblaze_1_local_memorythat has the Local Memory Bus, the Local Memory Bus Controller and the Block Memory Generator
- A Clocking Wizard
- An AXI Interconnect
- An AXI Interrupt Controller
Using Connection Automation
Because the design is not connected to any external I/O at this point, IP integrator offers the Connection Automation feature as shown in the light green banner of the design canvas in the preceding figure. When you click Run Connection Automation, IP integrator provides assistance in connecting interfaces and/or ports to external I/O ports.
The Run Connection Automation dialog box, shown in the following figure, lists the ports and interfaces that the Connection Automation feature supports, along with a brief description of the available automation, and available options for each automation.
For Xilinx Target Reference Platforms or evaluation boards, IP integrator has knowledge of the FPGA pins that are used on the target boards; this is called Board Awareness. Based on that information, the IP integrator connection automation feature can assist you in tying the ports in the design to external ports on the board. IP integrator then creates the appropriate physical constraints and other I/O constraints required for the I/O port in question.
In the MicroBlaze system design shown above, the following connections need to be made:
- Processor System Reset IP needs to be connected to an external reset port.
- Clocking Wizard needs to be connected to an external clock source as well as an external reset.
By selecting the appropriate options, as shown in the following figure, you can tie the clock and the reset ports to the appropriate sources on the target board.
You can select the reset pin that already exists on the KC705 target
board in this case, or you can specify a custom reset pin for your design. After the
reset is specified, the reset pin is tied to the
ext_reset_in pin of the
IP and the clock is connected to the on-board 200 MHz clock source called
The Designer Assistance feature is constantly monitoring your design development in IP integrator.
For example, assume that you instantiate the
AXI_GPIO IP into the design. The Run Connection Automation link
reappears in the banner on top of the design canvas. You can then click Run
Connection Automation and the
S_AXI port of the
newly added AXI GPIO can be connected to the MicroBlaze processor using the AXI
Likewise, the GPIO interface can be tied to one of the several interfaces present on the target board. (See the following figure.)
The connection options are as follows:
- The GPIO interface port can be connected to either the Dip Switches that are 4-bits, or to the LCD that are 7-bit or 8-bit, or the 5-bits of Push Buttons.
- The Rotary Switch on the board can be connected to a Custom interface.
Selecting any one of the choices connects the GPIO port to the existing connections on the board.
S_AXI interface for
automation, as shown in the following figure, informs you that the slave AXI port of
the GPIO can be connected to the MicroBlaze master. If there are multiple masters in
the design, then you have a choice to select between different masters. You can also
specify the clock connection for the slave interface such as
S_AXI interface of the GPIO.
When you click the OK in the Run Connection Automation dialog box, the connections are made and highlighted as shown in the following figure.
Using Enhanced Designer Assistance
Enhanced Designer Assistance is available for advanced users who want to connect an AXI4-Stream interface to a memory-mapped interface. In this case IP integrator instantiates the necessary sub-components and makes appropriate connections between them to implement this functionality. See this link in the Vivado Design Suite User Guide: Embedded Processor Hardware Design (UG898) for more information on this feature.