Configuration - 2022.1 English

Xilinx Standalone Library Documentation: BSP and Libraries Document Collection (UG643)

Document ID
UG643
Release Date
2022-04-21
Version
2022.1 English

The XilSEM library configuration options available through the CIPS v3.2 Customize IP dialog box in the Vivado Design Suite are shown in the following figure.

Figure 1. XilSEM Library Configuration within CIPS v3.2 Customize IP Dialog Box in Vivado Design Suite

From within CIPS, the fundamental feature of the XilSEM library can be enabled. This feature is the soft error mitigation of the configuration RAM through a scan-based process automated by integrated logic and managed by the XilSEM library, which reads back the configuration RAM and uses ECC and CRC to detect and correct soft errors. Some of the features of CRAM Scan can be configured through properties as shown in the following table.

Table 1. XilSEM CRAM Scan properties
Property Name Supported Values Default Value Description

CONFIG.PS_PMC_CONFIG

{SEM_MEM_ENABLE_SCAN_AFTER 1}

1 (Immediate start)

0 (Deferred start)

1 (Immediate start)

Immediate start: Enables automatic start of the configuration RAM scanning after boot.

Deferred start: Start of the scan during mission

The XilSEM library provides an optional feature for the soft error mitigation of NPI Registers, provided the supplemental hardware resources required for this feature are accessible. This feature is a scan-based process automated by integrated logic and managed by the XilSEM library, which reads back NPI Registers and uses SHA to detect errors. Some of the features of the NPI Scan can be configured thorough properties as shown in Table: XilSEM NPI Properties.

NPI Register scan requires XilSEM library use of PMC cryptographic acceleration. The following are some of the scenarios in which the XilSEM library cannot offer this optional feature:

  • User operation of the SHA block in the PMC for purposes of the user design
  • Device is programmed for “no end-user accessible” cryptographic functions
Use the following two mechanism to identify if cryptographic acceleration block is disabled in your device.
  • Read device Manual
  • During run time, XilSEM on PLM updates bit-31 in SEM_NPI_SCAN_STATUS register. The following bit status indicates if cryptographic acceleration block is present.
    • 0: cryptographic acceleration is present
    • 1: cryptographic acceleration is not present
  • If you try to perform NPI scan requests when cryptographic acceleration block is disabled, you will get error notification. CRAM scan has no relevance to cryptographic acceleration block and is functional.
Table 2. XilSEM NPI Properties
Property Name Supported Values Default Value Description
CONFIG.PS_PMC_CONFIG {SEM_NPI_ENABLE_SCAN_AFTER 0}

0 (Immediate start)

1 (Deferred start)

0 (Immediate start)

Immediate start: Enables automatic start of NPI scanning after boot.

Deferred start: Start of the NPI scan during mission based on your request.

BITGEN.GENERATESWSHA

False (HW SHA)

True (SW SHA)

True (SW SHA)

HW SHA: The value calculated during the first scan will be used as golden SHA.

SW SHA: Tool generated values are used as golden SHA for NPI scan.

CONFIG.PS_PMC_CONFIG {SEM_TIME_INTERVAL_BETWEEN_SCANS 80 } >=80 msec && <=1000 msec 80 msec The interval in milliseconds at which the NPI scan is repeated. Recommended to use 80 msec.

Additional XilSEM library properties as referenced below are available.

Table 3. Additional XilSEM Library Properties
Property Name Supported Values Default Value Description
CONFIG.PS_PMC_CONFIG {PMC_GPO_ENABLE 0}

0 (Disabled)

1 (Enabled)

0 (Disabled)

Disabled: PMC_PL_GPO will not be triggered for status and error information.

Enabled: PMC_PL_GPO will be triggered for status and error information.