#Define Xil_L1DCacheInvalidate - 2022.1 English

Xilinx Standalone Library Documentation: BSP and Libraries Document Collection (UG643)

Document ID
UG643
Release Date
2022-04-21
Version
2022.1 English

Description

Invalidate the entire L1 data cache.

If the cacheline is modified (dirty), the modified contents are lost.

Note: Processor must be in real mode.