The power metrics of the XilSEM library are not specified. However, the Xilinx Power Estimator (XPE) can be used to estimate XilSEM library power, which is mostly contributed by the configuration RAM scan process operated on the CFU clock domain. The CFU clock default frequency set by CIPS is high, to maximize bandwidth of the configuration RAM. Depending on design requirements, it may be desirable to operate at lower CFU clock frequencies.
CIPS currently supports user access to edit many clock generator settings, including the CFU clock. You can take advantage of this compile time tradeoff by lowering the CFU clock setting. This change, unless later overridden during design operation, will impact any CFU activity and that has broader implications than the XilSEM library. For example, other activities which use the CFU include (but are not limited to):
- PL Housekeeping at Boot
- Readback Capture and Verify
- DFX / Partial Reconfig
Using this compile time tradeoff is simple and can work well, especially with smaller devices where the bandwidth to size ratio of the configuration RAM might have ample margin versus design requirements to support trading it for power reduction. However, it is critically important to evaluate the broader impact of this tradeoff beyond XilSEM library power.