XilFPGA provides the following user configuration BSP settings.
| Parameter Name | Type | Default Value | Description |
|---|---|---|---|
| secure_mode | bool | TRUE | Enables secure Bitstream loading support. |
| debug_mode | bool | FALSE | Enables the Debug messages in the library. |
| ocm_address | int | 0xfffc0000 | Address used for the Bitstream authentication. |
| base_address | int | 0x80000 | Holds the Bitstream Image address. This flag is valid only for the Cortex-A53 or the Cortex-R5F processors. |
| secure_readback | bool | FALSE | Should be set to TRUE to allow the secure Bitstream configuration data read back. The application environment should be secure and trusted to enable this flag. |
| secure_environment | bool | FALSE | Enable the secure PL configuration using the IPI. This flag is valid only for the Cortex-A53 or the Cortex-R5F processors. |
| reg_readback_en | bool | TRUE | Enables the FPGA configuration Register Read-back support.(Note: From 2023.1 release onwards the default state will be changed to false). |
| data_readback_en | bool | TRUE | Enables the FPGA configuration Data Read-back support.(Note: From 2023.1 release onwards the default state will be changed to false) |
| get_version_info_en | bool | FALSE | Gets the Xilfpga library version info |
| get_feature_list_en | bool | FALSE | Gets the Xilfpga library supported feature list info |
| skip_efuse_check_en | bool | FALSE | Skips the eFUSE checks for PL configuration |