The Zynq UltraScale+ MPSoC VCU soft IP implements registers in the programmable logic. The following table summarizes the soft IP registers. These registers are accessible from the PS through the AXI4-Lite bus.
Register | Address Offset | Width | Type | Definition |
---|---|---|---|---|
VCU_ENCODER_ENABLE | 0x41000 | 32 | Ro |
|
VCU_DECODER_ENABLE | 0x41004 | 32 | Ro |
|
VCU_MEMORY_DEPTH | 0x41008 | 32 | Ro | Number of entries in Encoder Buffer |
VCU_ENC_COLOR_DEPTH | 0x4100C | 32 | Ro |
|
VCU_ENC_VERTICAL_RANGE | 0x41010 | 32 | Ro |
|
VCU_ENC_FRAME_SIZE_X | 0x41014 | 32 | Ro | Encoder horizontal pixel size |
VCU_ENC_FRAME_SIZE_Y | 0x41018 | 32 | Ro | Encoder vertical pixel size |
VCU_ENC_COLOR_FORMAT | 0x4101C | 32 | Ro |
|
VCU_ENC_FPS | 0x41020 | 32 | Ro | Denotes frames per second |
VCU_ENC_VIDEO_STANDARD | 0x41038 | 32 | Ro |
|
VCU_STATUS | 0x4103C | 32 | Ro |
These are the bit positions to be read for different status bits. |
VCU_DEC_VIDEO_STANDARD | 0x4104C | 32 | Ro |
|
VCU_DEC_FRAME_SIZE_X | 0x41050 | 32 | Ro | Decoder horizontal pixel size |
VCU_DEC_FRAME_SIZE_Y | 0x41054 | 32 | Ro | Decoder vertical pixel size |
VCU_DEC_FPS | 0x41058 | 32 | Ro | Decoder frames per second |
VCU_BUFFER_B_FRAME | 0x4105C | 32 | Ro |
|
ENC_NUM_CORE | 0x4106C | 32 | Ro | Number of encoders core used for the provided configuration |
VCU_PLL_CLK_HI | 0x41034 | 32 | Ro | Reports the integer value of PLL clock frequency as set in the Vivado block design. Each unit is 10 kHz. Default: 33.33 MHz |
VCU_PLL_CLK_LO | 0x41064 | 32 | Ro | Reports the fractional value of PLL clock frequency as set in the Vivado block design. Each unit is 10 kHz. Default: 33.33 MHz |
VCU_GASKET_INIT | 0x41074 | 32 | Rw |
Ensure there is no pending AXI transaction in VCU AXI bus/AXI4-Lite bus before accessing the register. Assert and de-assert Bit 0 is set to 1 to remove gasket isolation after VCUINT_VCU fully ramps, VCCAUX fully ramps, and the PL is programmed Bit 1 is set to 0 to assert reset to VCU. Software needs to de-assert it to 1 for out of resets. |