PLIO represents an ADF graph interface to the PL. This PL could be a PL
kernel, a platform IP representing a signal source or sink, or it could be a data
mover to interface the ADF graph to memory. You should provide clock frequency
values for these interfaces to ensure simulation results match the results from
running the design in hardware. In addition, when you link the ADF graph into the
platform, at the Vitis linker (
v++ -link) step, you have the ability to provide more
accurate clock values depending on the specific clock frequency values supported by
the platform. To set the exact frequency of a PLIO interface in the graph and the
clock frequency of the corresponding PL kernel you must specify the clock frequency
in three locations:
- ADF graph (Optional)
Vitis compilation of a PL kernel (
Vitis linking (
You must specify the clocking depending on where the kernels are located. The following table describes the default clocks based on the kernel location.
|AI Engine kernels||Clocked per the AI Engine clock frequency. All cores run with the same clock frequency.|
|PL kernels connected to AI Engine graph||HLS: Default frequency for all HLS kernels - 150 MHz
RTL: Frequency is set to the frequency that the XO file was compiled with.
AI Engine: Set in the PLIO constructor in the AI Engine graph. Setting the frequency here is optional. See Adaptive Data Flow Graph Specification Reference for more information. 1
|PL kernels added to platform using the Vitis linker||Platforms have a default clock. If no clocking option is set at the command line or configuration file the default clock is used. This default can be overridden depending on the design and required clock value, as shown in the following table.|
Setting the clocks at the Vitis linker step allows you to choose a frequency based on the platform. The following table describes the Vitis compiler clocking options during the link step.
||Specify a default clock frequency to use in Hz.|
||Specify a default clock reference ID to use.|
||Specify a default clock tolerance to use.|
Specify a clock frequency in Hz and a list of associated compute unit names and optionally their clock pins.
Specify a clock reference ID and a list of associated compute unit names and optionally their clock pins.
Specify a clock tolerance and a list of associated compute unit names and optionally their clock pins.
The following table describes the steps to set clock frequencies for PLIOs that interface to the platform, including to PL kernels specified outside of the ADF graph.
|PL Kernel Location||Clock Specification|
|PLIO interface specified in ADF graph||Specify the clock frequency per PLIO interface in the graph.
For the PLIO interface, you can optionally
|HLS kernels||Compile the HLS code using the Vitis compiler.
change the frequency at which HLS kernels are compiled use:
Per kernel, specify the clock in the Vitis linker.
|RTL kernels||Per kernel, specify the clock in the Vitis
See Vitis Unified Software Platform Documentation: Application Acceleration Development (UG1393) for more detailed information on how to compile kernels for specific platform clocks and clocking information.