The DMA FIFO size can be viewed in the timeline in Vitis Analyzer
using VCD-based analysis. Vitis Analyzer shows the real-time used FIFO depth. From
the FIFO depth used, Vitis Analyzer can help analyze design stall issue, optimize
FIFO size needed, and then optimize the design performance.
Note: Stream Switch FIFO size is not
supported.
For enabling DMA FIFO size visualization, the VCD dump option of
aiesimulator should be enable. Also, the
simulation run result can be opened in Vitis Analyzer, for
example:aiesimulator --pkg-dir=./Work --online -wdb -ctf
vitis_analyzer aiesimulator_output/default.aierun_summaryFor more options on how to run simulator and open run result in Vitis Analyzer, see AI Engine Stall Analysis in Vitis Analyzer.
Tip: If design hangs in simulation, use the
--simulation-cycle-timeout=<cycles> option to
stop the aiesimulator simulation at a set
time.In Vitis Analyzer, select the Graph view and select the DMA FIFO in the view.
Tip: Hover the mouse on the DMA FIFO to show
information about the DMA FIFO, such as, the FIFO depth in words.
The following figure shows an example of DMA FIFO in Graph view:
Figure 1. DMA FIFO in the Graph View
The selected DMA FIFO in the Graph view is also highlighted in the Trace view. You must switch to the Trace view.
The DMA FIFO size in words is shown in the timeline, as shown in the following
figure. In the Events view, it contains DMA_FIFO_SIZE event with the size information
Figure 2. DMA FIFO in the Trace View