Designs running on Versal® AI Engine devices can target the AI Engine, PL, and Arm® host. To ensure a design targeting such multi-domain devices is functionally correct and meets the design performance specification, Xilinx® recommends a five-stage profile and debug methodology in hardware.
The stages are as follows:
- Design Execution and System Metrics
- System Profiling
- PL Kernel Analysis
- AI Engine Event Trace and Analysis
- Host Application Debug
Figure 1. Five Stages of Profile and Debug Methodology
The goal of each stage along with available tools and techniques are described below.