When it targets the X86 simulation, the AI Engine compiler does not use the complete hardware architecture of the AI Engine in order to create the executable. Actually there is no place and route phase of the various kernels and a single executable is generated.
As the array architecture of the device is not used, the routing delay cannot be modeled in the x86 simulation. In the same order, FIFO length won't be simulated.
X86 simulations are composed of multiple threads sharing the X86 processor. That's why memory access conflicts and stream access conflict won't be modeled.
When compiling with X86 simulation target, the AI Engine compiler will translate all vector processor specific instructions into a series of X86 instructions hence the inability to have any kind of throughput estimate of a kernel. Furthermore, the effect of software pipelining won't be simulated during X86 simulation.