After the AI Engine graph and
the C/C++ kernels are compiled, and any RTL kernels are packaged, the Vitis
v++ --link command links them with the target
platform to build the platform file (XSA), used to package the design. For more
Linking the Kernels in
the Application Acceleration Development flow of the Vitis Unified Software Platform
The following is an example of the linking command for the Vitis compiler in the AI Engine design flow.
v++ --link -t hw_emu --platform xilinx_vck190_base_202210_1 -g \ <pl_kernel1>.xo <pl_kernel2>.xo ../libadf.a -o vck190_aie_graph.xsa \ --config ../system.cfg --save-temps
v++ command uses the options
in the following table.
||Specifies the linking process.|
||Specifies the build target of the link process.
For the AI Engine kernel flow,
the target can be either
Important: The v++ compilation and linking commands must use both the same build target (
||Specifies the path to the target platform.|
||Specifies the addition of debugging logic required to enable debug (for hardware emulation) and to capture waveform data.|
||Specifies the input compiled PL kernel object
||Specifies the input compiled AI Engine graph application to link with the PL kernels and the target platform.|
||Specifies the platform (XSA) file that is the output of the linking process.|
||Specifies a configuration file to define some of the compilation or linking options. 1|
||Indicates that the temporary files created during the build process should be preserved for later examination or use. This includes output files created by Vitis HLS and the Vivado Design Suite.|
For the AI Engine kernel flow,
the Vitis compiler requires one specific
section in the configuration file:
The following is an example configuration file.
[connectivity] nk=mm2s:1:mm2s nk=s2mm:1:s2mm stream_connect=mm2s.s:ai_engine_0.DataIn1 stream_connect=ai_engine_0.DataOut1:s2mm.s
[connectivity] section of the
configuration file has options described in the following table.
||Specifies the number of kernel- instances or CUs the
Multiple instances of
the kernels are specified as
||Defines AXI4-Stream connections between the ports of the
AI Engine graph and the
streaming ports of the PL kernels. Connections can be defined as the
streaming output of one kernel connecting to the streaming input of
a second kernel, or to a streaming input port on an IP implemented
in the target platform. For more information, see
in the Vitis Unified Software Platform
Documentation: Application Acceleration Development
During the linking process, the Vitis compiler invokes the Vivado Design Suite to generate the platform file (XSA) for the target platform. The XSA file is used to package the design and includes the following information.
- Programming information for the AI Engine array
- Debug data
- Debug information when included in the build
- Memory topology
- Defines the memory resources and structure for the target platform
- IP Layout
- Defines layout information for the implemented hardware design
- Various elements of platform meta data to let the tool load and run the XCLBIN file on the target platform
For more information on the XRT use of the XCLBIN file, see XRT.