The AI Engine array interface contains modules to communicate between AI Engines and PL kernels using AXI4-Stream connections. Generally, PL interfaces produce or consume data through stream interfaces. They connect through the AI Engine stream with AI Engine kernels. Based on whether window or stream data is communicated by the AI Engine kernels, DMA and ping-pong buffers could be involved.
Note that PL kernels run at a lower frequency than AI Engine kernels. Data must cross the clock domains (CDC) between the AI Engine clock and PL clock. The Vitis™ environment handles the CDC path automatically. It is recommended to run the PL kernel frequency as an integer factor of the AI Engine frequency if possible. For instance, as ½ or ¼ of the AI Engine clock frequency.
For more information about AI Engine to PL rate matching considerations, refer to the Versal ACAP AI Engine Programming Environment User Guide (UG1076).