DFX Support - 2022.1 English

PetaLinux Tools Documentation: Reference Guide (UG1144)
Document ID
UG1144
Release Date
2022-04-26
Version
2022.1 English

This section will help to build and boot DFX(single slot) design for Versal® platforms.

  1. Source the PetaLinux tool
  2. Create a Versal template project.

    $ petalinux-create -t project -n versal-dfx  --template versal

  3. $ cd versal-dfx
  4. Enable petalinux-config → FPGA_MANAGER
  5. Use the petalinux-create command to create the recipe file for static xsa/design

    $ petalinux-create -t apps --template fpgamanager_dtg -n <static-app> --enable --srcuri "<path>/<static.xsa> <path>/shell.json"

    The above command will create the fpgamanager_dtg with static xsa file to generate the static dtbo, pdi files and install into the rootfs (/lib/firmware/xilinx/<static-app>).
    Note: Passing the shell.json is optional if you use fpgautil to load. If you use dfxmgr then it is required.
    Note: In 2022.1 due to Yocto limitation PetaLinux doesn’t generate UID and PID node properties for static xsa in static dtsi file as UID and PID are optional properties in FPGA drivers and it doesn't affect the functionality. We might fix this in next release.
  6. Use the petalinux-create command to create the recipe file for rprm xsa/design. We should point static pl app name to --static-pn command line option.

    $ petalinux-create -t apps --template fpgamanager_dtg_dfx -n <rprm-app> --enable --srcuri "<path>/<rprm.xsa> <path>/accel.json" --static-pn <static-app>

    The above command will create the fpgamanager_dtg_dfx with rprm xsa file to generate the rprm dtbo, pdi files and install into the rootfs (/lib/firmware/xilinx/<static-app>/<rprm-app>).
    Note: Passing the accel.json is optional if you use fpgautil to load. If you use dfxmgr then it is required.

  7. 7. By default DTG doesn't generate firmware-name device tree node property when we pass external firmware-pdi name from yocto hence we need do_configure workaround solution for partial recipe in 2022.1 release.

    open <versal-dfx>/project-spec/meta-user/recipes-apps/rprm-app.bb 

    # By default DTG doesn't generate firmware-name property hence we need this workaround solution for 2022.1 release.
do_configure:append() {
  if ls ${B}/${XSCTH_PROJ}*inst_0.dtsi >/dev/null 2>&1; then
# Workaround solution to add partial firmware name.
 sed -i '/partial-fpga-config/i firmware-name = "${PN}.pdi";' $(ls ${B}/${XSCTH_PROJ}*inst_0.dtsi 2&gt; /dev/null)
 fi
}

    petalinux-build

    The command will generate the rootfs containing the both static, rprm dtbos and respective pdi files as mentioned in the step 4 and step 5 paths.

    Once the base boot images ready with the above step, if you want to build only dfx apps then use the following commands:

    petalinux-build -c <static-app>
petalinux-build -c <rprm-app>
in below path you will the rpms with the below names.
in <TMPDIR>/deploy/rpm you will see <static-app>.rpm and <rprm-app>.rpm
Note: The pdi's in the design should have i*_partial.pdi in the xsa files, other wise it will through an error.
Note: In DFX use case we use the static xsa to create the Versal boot firmware images so static pdi is packaged as part of BOOT.BIN.

Boot Steps

Up the target with above built images using any of the boot methods in the documentation. Once the target is up.
vck190-dfx:/home/petalinux# fpgautil -o /lib/firmware/xilinx/<static-app>/<static-app>.dtbo
[ 71.571728] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /fpga/external-fpga-config
[ 71.582142] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/overlay0
[ 71.592010] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/fpga_PR0
[ 71.601854] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/overlay2
[ 71.611688] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/static_shell_SIHA_Manager_0
[ 71.623169] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/static_shell_axi_gpio_0
[ 71.634302] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/static_shell_axi_intc_0
[ 71.645435] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/static_shell_clk_gen_clk_wizard_0
[ 71.660647] of-fpga-region fpga:fpga-PR0: FPGA Region probed
[ 71.667512] irq-xilinx: mismatch in kind-of-intr param
[ 71.672705] irq-xilinx: /axi/interrupt-controller@a4060000: num_irq=32, sw_irq=0, edge=0xffffffff
vck190-dfx:/home/petalinux#
vck190-dfx:/home/petalinux# fpgautil -b /lib/firmware/xilinx/<static-app>;/rp0/<rprm-app>/<rprm-app>.pdi -o /lib/firmware/xilinx/<static-app>/rp0/<rprm-app>/<rprm-app>.dtbo -f Partial -n PR0
[ 142.795102] fpga_manager fpga0: writing opendfx-rp0-aes128.pdi to Xilinx Versal FPGA Manager
[152814.496]Loading PDI from DDR
[152814.609]Monolithic/Master Device
[152817.904]3.383 ms: PDI initialization time
[152821.876]+++Loading Image#: 0x0, Name: pl_cfi, Id: 0x18700000
[152827.520]---Loading Partition#: 0x0, Id: 0x103
[152831.949] 0.046 ms for Partition#: 0x0, Size: 28560 Bytes
[152837.180]---Loading Partition#: 0x1, Id: 0x105
[152841.567] 0.005 ms for Partition#: 0x1, Size: 32 Bytes
[152846.582]---Loading Partition#: 0x2, Id: 0x205
[152851.076] 0.112 ms for Partition#: 0x2, Size: 2064 Bytes
[152856.156]---Loading Partition#: 0x3, Id: 0x203
[152860.565] 0.027 ms for Partition#: 0x3, Size: 544 Bytes
[152865.643]---Loading Partition#: 0x4, Id: 0x303
[152875.331] 5.304 ms for Partition#: 0x4, Size: 3238160 Bytes
[152878.011]---Loading Partition#: 0x5, Id: 0x305
[152882.801] 0.406 ms for Partition#: 0x5, Size: 7296 Bytes
[152887.586]---Loading Partition#: 0x6, Id: 0x403
[152892.020] 0.051 ms for Partition#: 0x6, Size: 49312 Bytes
[152897.246]---Loading Partition#: 0x7, Id: 0x405
[152901.633] 0.005 ms for Partition#: 0x7, Size: 32 Bytes
[152906.697]Subsystem PDI Load: Done
[ 142.904337] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/overlay0RP_0_AES128_inst_0
[ 142.918020] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/overlay2_RP_0_AES128_inst_0
[ 142.929504] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/RP_0_AccelConfig_0
[ 142.940202] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/misc_clk_RP_0_AES128_inst_00
[ 142.951768] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/RP_0_axi_gpio_0
[ 142.962208] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/RP_0_rm_comm_box_0
[ 142.975851] gpio-xilinx 20100010000.gpio: #gpio-cells mismatch
[ 142.981709] gpio-xilinx: probe of 20100010000.gpio failed with error -22
Time taken to load BIN is 196.000000 Milli Seconds
BIN FILE loaded through FPGA manager successfully
vck190-dfx:/home/petalinux#