PL kernels can also be developed using RTL kernels and the Vivado Design Suite. This approach is convenient for hardware engineers that have existing RTL IP, including Vivado IP integrator-based designs, or prefer creating new functions by writing RTL code.
An RTL kernel is a regular design packaged as Vivado Design Suite IP, but the kernel must comply with specific interface rules and requirements to be usable in the Vitis environment design flow. For more information about RTL kernels, see this link in the Vitis Unified Software Platform Documentation: Application Acceleration Development (UG1393).
Creating an RTL kernel follows traditional RTL design guidelines. Xilinx highly recommends that you create dedicated test benches and use behavioral simulation to thoroughly verify the RTL code before packaging and using the code as PL kernels in the Vitis environment design flow. After an RTL design is fully verified and meets all the requirements for a Vitis kernel, the design can be packaged into a Vitis kernel object (XO file) using the Vivado IP packager.
For more information on how to develop and simulate RTL kernels, see the Create PL Kernels Using RTL section of the Versal ACAP Design Process Documentation: Hardware, IP, and Platform Development Guided - Platform.