Multiplexed I/O - 2022.1 English

Versal ACAP Design Guide (UG1273)

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2022.1 English

The Versal ACAP multiplexed I/O (MIO) are similar to the MIO on the Zynq UltraScale+ MPSoCs. In Versal devices, there are 78 MIO pins, 52 signals in the PMC MIO (banks 500 and 501), and 26 signals in the LPD MIO (bank 502). For details on MIO pin planning, see this link and this link in the Versal ACAP Technical Reference Manual (AM011). The Versal ACAP Control, Interfaces, and Processing System (CIPS) IP is used to select the MIOs to use and specify their functionality.