The Versal architecture includes several blocks for implementation of high-performance, standards-based interfaces built on PCI™ -SIG technologies. In addition to the integrated CPM blocks, the Versal architecture includes support for implementation of PCIe® in the PL. PL PCIe are significantly enhanced implementations of the integrated blocks for PCIe found in previous architectures.
If your design needs to be migrated from an integrated block for PCIe in a previous architecture to a Versal ACAP PL PCIe® block, consider the following:
- Only the Vivado IP integrator-based block design flow is currently supported with manual or automatic connectivity.
- The required GT and PHY IP blocks for Versal ACAP PL PCIe are outside of the Versal ACAP PL PCIe® block.
- Configure the PCIe subsystem with the required link speed, width, and features using the PL PCIe® block, and either run block automation or instantiate and connect the required GT and PHY IP manually.
- Xilinx recommends driving fundamental reset for the PCIe controller using the I/O inside the processing system, which must be configured in the CIPS IP.
- Manually map RQ/RC/CQ/CC streaming interfaces and side band signals, which are similar to their respective IP implementation from previous architectures.
If your design needs to be migrated from an integrated block for PCIe in a previous architecture to a Versal architecture CPM block, consider the following:
- Configure the PCIe subsystem with the required link speed, width, and features in the CPM using the CIPS IP core.
- Fundamental reset for the PCIe controller is driven by the I/O inside the processing system, which must be configured in the CIPS IP.
- Only user_clk, which can have a frequency of 62.5, 125, or 250 MHz depending on the configured link speed and width, is available for the programmable logic.
- Manually map RQ/RC/CQ/CC streaming, sideband signals, XDMA streaming, and QDMA streaming interfaces to Versal ACAP CPM PL interfaces. These interfaces are similar to their respective IP implementation from previous architectures.
- Manually map the AXI4 memory-mapped (AXI4-MM) interfaces, including the AXI4-MM bridge, Xilinx DMA memory-mapped (XDMA-MM) interface, and Queue DMA memory-mapped (QDMA-MM) interface, into the NoC infrastructure. This requires setting up various components in the design, such as the NoC, processing system, address translation, and address allocation.
For more information, see the following documents for devices with CPM:
- Versal ACAP Integrated Block for PCI Express LogiCORE IP Product Guide (PG343)
- Versal ACAP DMA and Bridge Subsystem for PCI Express Product Guide (PG344)
- Versal ACAP PCIe PHY LogiCORE IP Product Guide (PG345)
- Versal ACAP CPM Mode for PCI Express Product Guide (PG346)
- Versal ACAP CPM DMA and Bridge Mode for PCI Express Product Guide (PG347)