Power and Error Handling - 2022.1 English

Versal ACAP Design Guide (UG1273)

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2022.1 English

Zynq UltraScale+ MPSoCs have some power modes that can be mapped to the power modes in Versal ACAP. Peripherals that are power islands are shared in the Versal ACAP. When not in use, these power islands are automatically turned off by the PLM. Many main external power rails that supply power domains are currently supported for sleep states. Additional support will be added in future releases. In Zynq UltraScale+ MPSoCs and Versal ACAPs, PL power management methodology is similar and offers the largest power benefit. For more information, see this link in the Versal ACAP Board System Design Methodology Guide (UG1506). In Versal ACAP, errors from the DDR, PL, SYSMON, and other system blocks are routed to the PMC error aggregation module (EAM), and the PS errors are routed to the EAM in the PS management controller (PSM). Possible error actions are power-on reset (POR), system reset (SRST), error out, or interrupt software agents.

For detailed architectural differences, see the Versal ACAP Technical Reference Manual (AM011) and Versal ACAP System Software Developers Guide (UG1304).