The Versal ACAP APU provides improved performance at an improved safety level. However, for real-time applications which require a higher level of safety (e.g., ASIL-C/SIL3), reliability, and determinism, real-time processing unit (RPU) is used with a lockstep processor subsystem.
The RPU architecture specification consists of RPU cores, TCMs, and on-chip memory. The following list describes the main RPU features.
- Dual 32-bit Cortex-R5F cores based on Arm v7-R architecture and supports lock-step or split mode options
- 128 KB TCM per Cortex-R5F processor in split mode.
- Option to combine 256 KB of TCM in lock-step mode.
- 256 KB of on-chip memory with error correction code (ECC) accessible by both the RPU and the APU.
- 32 KB L1 instruction cache with error correction code (ECC) or parity and 32 KB L1 data cache with error correction code (ECC)
- Generic interrupt controller (GIC) to support GIC architecture
- Per lock-step power-gating support
- TCM and OCM power-gating
- TrustZone aware