Versal DFX Management - 2022.1 English

Versal ACAP System Software Developers Guide (UG1304)

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2022.1 English

It is possible to confgure the PL configuration at run time from baremetal and Linux-like operating systems. The PL configuration data for Versal ACAP can be accessed as PDI files. For baremetal/FreeRTOS applications, the “xilfpga” library can be used for programming the PL configuration data. For more details, see OS and Libraries Document Collection (UG643). From Linux, the FPGA Manager in Versal ACAP provides an interface to download PL configuration data (DFX) at run time from Linux. This PL configuration data or DFX image is a PDI which can be either authenticated/encrypted or both or can be non-secure.

Note: You have to use a DFX flow to load the PL through an application or U-Boot/Linux.

The following figure shows the PL configuration flow for Linux.

Figure 1. PL Configuration Flow from Linux

To load a PDI with PL configuration data, the FPGA manager allocates the required memory and invokes the EEMI API using the FPGA LOAD API ID. This request is a blocking call. The FPGA manager waits for the response from the TF-A and response is provided to the FPGA manager core layer which passes it to the application. At the application layer, Xilinx provides two user space utilities, namely fpgautils and libdfx for programming the PL configuration data.

fpgautils is a legacy and developer friendly Linux user space utility for programming the PL configuration data from command line. Unlike fpgautils, libdfx is a C library that can be integrated into user applications. It provides different APIs that can address multiple use cases for DFX or PL configuration data programming. It also provides faster programming capability by avoiding multiple buffer copies that are involved in other methods. For more information on libdfx and its usage, refer to the libdfx repo. An example application for programming the PL configuration data is available in the apps/ directory.