Primitive: I/O Weak Keeper
- PRIMITIVE_GROUP: I/O
- PRIMITIVE_SUBGROUP: WEAK_DRIVER
The design element is a weak keeper element that retains the value of the I/O when not being driven. For example, if a logic 1 is being driven onto the I/O, KEEPER drives a weak/resistive 1 onto the pin/port. If the net driver is then 3-stated, KEEPER continues to drive a weak/resistive 1 onto the pin/port.
|O||Inout||1||Keeper output. Connect directly to a top_level port.|
Design Entry Method
|Inference||Yes, via property|
|IP and IP Integrator Catalog||No|
VHDL Instantiation Template
Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM; use UNISIM.vcomponents.all;
-- KEEPER: I/O Weak Keeper -- Versal Prime series -- Xilinx HDL Language Template, version 2022.1 KEEPER_inst : KEEPER port map ( O => O -- 1-bit inout: Keeper output (connect directly to top-level port) ); -- End of KEEPER_inst instantiation
Verilog Instantiation Template
// KEEPER: I/O Weak Keeper // Versal Prime series // Xilinx HDL Language Template, version 2022.1 KEEPER KEEPER_inst ( .O(O) // 1-bit inout: Keeper output (connect directly to top-level port) ); // End of KEEPER_inst instantiation
- Versal ACAP SelectIO Resources Architecture Manual (AM010)