Primitive: 1-Bit Look-Up Table
- PRIMITIVE_GROUP: CLB
- PRIMITIVE_SUBGROUP: LUT
This design element is a 1-bit look-up table (LUT). This element provides a look-up table version of a buffer or inverter.
The INIT parameter for the LUT primitive is what gives the LUT its logical value. By default, this value is zero, thus driving the output to a zero regardless of the input values (acting as a ground). However, in most cases a new INIT value must be determined in order to specify the logic function for the LUT primitive. There are at least two methods by which the LUT value can be determined:
- The Logic Table Method: A common method to determine the desired INIT value for a LUT is using a logic table. To do so, simply create a binary logic table of all possible inputs, specify the desired logic value of the output and then create the INIT string from those output values.
- The Equation Method: Another method to determine the LUT value is to define parameters or generics for each input to the LUT that correspond to their listed truth value and use those to build the logic equation you are after. This method is easier to understand once you have grasped the concept and is more self-documenting than the above method. However, this method does require the code to first specify the appropriate parameters or generics.
A LUT1 can be grouped with another LUT1, LUT2, LUT3, or LUT4 and placed into a single LUT6 resource. It can also be placed with a LUT5; however, it must share a common input signal. The Vivado Design Suite will automatically combine LUTs when necessary or advantageous. However, this can be manually controlled by specifying a LUTNM or HLUTNM on the associated LUT components to specify specific grouping within a single LUT resource.
|INIT = Binary number assigned to the INIT attribute|
Design Entry Method
|IP and IP Integrator Catalog||No|
|INIT||HEX||2'h0 to 2'h3||2'h0||Specifies the logical expression of this element.|
VHDL Instantiation Template
Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM; use UNISIM.vcomponents.all;
-- LUT1: 1-Bit Look-Up Table -- Versal AI Core series -- Xilinx HDL Language Template, version 2022.1 LUT1_inst : LUT1 generic map ( INIT => X"0" -- Logic function ) port map ( O => O, -- 1-bit output: LUT I0 => I0 -- 1-bit input: LUT ); -- End of LUT1_inst instantiation
Verilog Instantiation Template
// LUT1: 1-Bit Look-Up Table // Versal AI Core series // Xilinx HDL Language Template, version 2022.1 LUT1 #( .INIT(2'h0) // Logic function ) LUT1_inst ( .O(O), // 1-bit output: LUT .I0(I0) // 1-bit input: LUT ); // End of LUT1_inst instantiation
- Versal ACAP Configurable Logic Block Architecture Manual (AM005)