Primitive: 512-Deep by 1-Wide Random Access Memory (Select RAM)
- PRIMITIVE_GROUP: CLB
- PRIMITIVE_SUBGROUP: LUTRAM
This design element is a 512-bit deep by 1-bit wide random access memory with synchronous write and asynchronous read capability. This RAM is implemented using the LUT resources of the device (also known as Select RAM), and does not consume any of the block RAM resources of the device. If a synchronous read capability is preferred, a register can be attached to the output and placed in the same slice as long as the same clock is used for both the RAM and the register. The RAM512X1S has an active-High write enable, WE, so that when that signal is High, and a rising edge occurs on the WCLK pin, a write is performed recording the value of the D input data pin into the memory array. The output O displays the contents of the memory cell addressed by A, regardless of the WE value. When a write is performed, the output is updated to the new value shortly after the write completes.
|O||Output||1||Read/Write port data output addressed by A|
|D||Input||1||Write data input addressed by A|
|A||Input||9||Read/Write port address bus|
|WCLK||Input||1||Write clock (reads are asynchronous)|
Design Entry Method
If instantiated, the following connections should be made to this component:
Tie the WCLK input to the desired clock source, the D input to the data source to be stored, and the O output to an FDCE D input or other appropriate data destination.
Connect the WE clock enable pin to the proper write enable source in the design.
Connect the 8-bit A bus to the source for the read/write.
You can use the INIT attribute to specify the initial contents of the RAM. If left unspecified, the initial contents default to all zeros.
|INIT||HEX||Any 512-bit value||All zeros||Specifies the initial contents of the RAM.|
|IS_WCLK_INVERTED||BINARY||1'b0 to 1'b1||1'b0||Specifies whether or not to use the optional inversion on the WCLK pin.|
VHDL Instantiation Template
Library UNISIM; use UNISIM.vcomponents.all;
-- RAM512X1S: 512-deep by 1-wide positive edge write, asynchronous read -- single-port distributed LUT RAM -- Versal AI Core series -- Xilinx HDL Language Template, version 2022.1 RAM512X1S_inst : RAM512X1S generic map ( INIT => X"00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", -- Initial contents of RAM IS_WCLK_INVERTED => '0') -- Specifies active high/low WCLK port map ( O => O, -- Read/Write port 1-bit ouput A => A, -- Read/Write port 9-bit address input D => D, -- RAM data input WCLK => WCLK, -- Write clock input WE => WE -- Write enable input ); -- End of RAM512X1S_inst instantiation
Verilog Instantiation Template
// RAM512X1S: 512-deep by 1-wide positive edge write, asynchronous read (Mapped to eight LUT6s) // single-port distributed LUT RAM // Versal AI Core series // Xilinx HDL Language Template, version 2022.1 RAM512X1S #( .INIT(512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), .IS_WCLK_INVERTED(1'b0) // Specifies active high/low WCLK ) RAM512X1S_inst ( .O(O), // Read/write port 1-bit output .A(A), // Read/write port 9-bit address input .WE(WE), // Write enable input .WCLK(WCLK), // Write clock input .D(D) // RAM data input ); // End of RAM512X1S_inst instantiation
- Versal ACAP Configurable Logic Block Architecture Manual (AM005)