During the following phases, the Vivado placer determines the placement of MMCM/XPLL/DPLLs, global clock buffers, and the clock root while honoring the physical XDC constraints:
- I/O and clock placement
The placer places I/O buffers and MMCM/XPLL/DPLLs based on connectivity rules and user constraints. The placer assigns clock buffers to clock regions but not to individual sites unless constrained using the LOC property. Only the clock buffers that drive non-clock loads can move to a different clock region later in the flow based on the placement of their driver and loads.
Any placer error at this phase is due to conflicting connectivity rules, user constraints, or both. The log file shows extensive information about the possible root cause of the error, which you must review in detail to make the appropriate design or constraint change.
- Clock tree pre-routing
The placer guides the subsequent implementation steps and provides accurate delay estimates for post-place timing analysis.
After placement, the Vivado tools can modify the clock tree implementation as follows:
- The Vivado physical optimizer can replicate and move cells to clock regions without associated clocks within the clock expansion window for the clock net.
- The Vivado router can make adjustments to improve timing QoR and legalize the clock routing.