In addition to specifying the location and I/O standard for each port of the design, input and output delay constraints must be specified to describe the timing of external paths to/from the interface of the device. These delays are defined relative to a clock that is usually also generated on the board and enters the device. In some cases, the delays must be defined related to a virtual clock when the I/O path is related to a clock that has a waveform different from the board clock.
Important: I/O delays can only be constrained for interfaces using I/O logic, such as IDDR/ODDR/IOB registers or fabric. For high-speed I/O interfaces in Versal ACAP, Xilinx provides the Advanced IO Wizard and Advanced I/O Planner. The Advanced IO Wizard configures the XPHY and can be used to estimate the I/O timing for the interface. For more information about the Advanced IO Wizard, see the Advanced I/O Wizard LogiCORE IP Product Guide (PG320).