You can package HDL sources into an IP using the Vivado IP packager for use in a block design. The packaged IP can comprise RTL sources, a block design, or a mix of the two. Packaged IP gives you control over the vendor, library, name, and version (VLNV). However, you cannot edit the RTL source files for a packaged IP, and the content inside a packaged IP is not visible to the block design it is instantiated in. To ensure proper functionality of your custom IP, Xilinx recommends that you follow the requirements explained in the Vivado Design Suite User Guide: Creating and Packaging Custom IP (UG1118).
Following is important information to note when using custom packaged IP:
- Packaging output loses addressing information. However, you can customize the addressing of the packaged IP within IP packager. For more information, see the Vivado Design Suite User Guide: Creating and Packaging Custom IP (UG1118).
- SmartConnect address information is fixed, and only the generated HDL is packaged. If you want to leverage the dynamic addressing capability of SmartConnect, either place the IP should directly on the IP integrator canvas or instance the IP within a block design container.
- The IP packager output does not provide access to parameter propagation. However, the IP packager can be guided by pragmas.
- The IP packager does not support associated ELF files for simulation but does support associated ELF files with synthesis.
The following figure shows the design hierarchy for a user-packaged IP that contains user RTL source files.