Versal devices have a significantly different architecture from previous devices, which requires special considerations when defining your design hierarchy. Planning your hierarchy early in the design process helps to minimize issues later. In Versal devices, the software must operate in conjunction with the hardware. To ensure a seamless hardware handoff from the Vivado Design Suite to the Vitis environment, follow these recommendations when defining your design hierarchy:
- Contain the addressable portions of your design in a single BD
hierarchy.
Addressable portions of your design include CIPS, NoC, transceivers, MicroBlaze™ processors, and any other addressable elements. The BD can be at the top of your design hierarchy (with a Xilinx-managed top-level RTL wrapper), or the BD can be instanced in the top level of your custom RTL. If you incorporate other IP into your block design using any of the methods included in this chapter, use methods that support hardware handoff. For example, using block design containers to compartmentalize and partition your design works in conjunction with hardware handoff. However, if you use RTL module referencing, then the addressing information is not preserved. It is important to consider these restrictions early in the design process.
- If you plan to boot the processing sub-system first and then load the PL
programming later, include the CIPS and the NoC at the top level of your design and
the PL portion of your design in a block design container (BDC).
For information on the Classic SoC Boot design methodology, see the Vivado Design Suite User Guide: Dynamic Function eXchange (UG909).