Design Creation with Vitis HLS - 2022.1 English

Versal ACAP Hardware, IP, and Platform Development Methodology Guide (UG1387)

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2022.1 English

Vitis™ HLS is a high-level synthesis tool that allows C, C++, and OpenCL™ functions to become hardwired onto the device logic fabric and RAM/DSP blocks. Vitis HLS implements hardware kernels in the application acceleration development flow and uses C/C++ code for developing RTL IP for Xilinx® device designs in the Vivado® Design Suite.

In the Vitis application acceleration flow, the Vitis HLS tool automates much of the code modifications required to implement and optimize the C/C++ code in programmable logic and to achieve low latency and high throughput. The inference of required pragmas to produce the right interface for your function arguments and to pipeline loops and functions within your code is the foundation of Vitis HLS in the application acceleration flow. Vitis HLS also supports customization of your code to implement different interface standards or specific optimizations to achieve your design objectives.

Following is the Vitis HLS design flow:

  1. Compile, simulate, and debug the C/C++ algorithm.
  2. View reports to analyze and optimize the design.
  3. Synthesize the C algorithm into an RTL design.
  4. Verify the RTL implementation using RTL co-simulation.
  5. Package the RTL implementation into a compiled object file (.xo) extension, or export to an RTL IP.