Design Planning Considerations for Classic SoC Boot - 2022.1 English

Versal ACAP Hardware, IP, and Platform Development Methodology Guide (UG1387)

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2022.1 English

Classic SoC Boot is a solution that enables designers to boot the processors in the Scalar Engines of a Versal device and access DDR memory before the programmable logic (PL) in the Adaptable Engines is configured. This allows DDR-based software like Linux to boot first followed by the PL, which can be configured later if needed via any primary or secondary boot device or through a DDR image store. The Classic SoC Boot feature is intended to treat Versal boot sequences similar to Zynq UltraScale+ MPSoCs.

This solution is built using a Dynamic Function eXchange (DFX) flow through the Vivado IP integrator, which includes automatic floorplan generation and flow-specific design rule checks (DRCs). The entire PL is dynamic and can be completely reloaded while any operating system and DDR memory access remain active.

When using Classic SoC Boot, you must consider the following when planning your design:

  • The CFI logic used to program the PL at a later phase is built as a partial programmable device image (PDI). Therefore, you must arrange the PL for your design hierarchically inside a reconfigurable partition (RP) in the netlist.
  • The PS-PL isolation is controlled by the partial PDI. Therefore, you do not need to add the DFX Decoupler to the static region of the netlist.
  • Classic SoC Boot automatically pulls the top-level I/O buffers (IBUF and OBUF) directly connected to the RP into the logical hierarchy. You must instantiate any other types of I/O buffers inside the RP.
  • The Vivado tools automatically create the Pblock for the RP for Classic SoC Boot. However, if you provided a Pblock constraint, your Pblock constraint is honored and automatic Pblock creation does not occur.

For more information, see the Classic Soc Boot Tutorial available from the Xilinx GitHub repository.