Design Planning Considerations for Dynamic Function eXchange - 2022.1 English

Versal ACAP Hardware, IP, and Platform Development Methodology Guide (UG1387)

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2022.1 English

Dynamic Function eXchange (DFX) requires special planning considerations for traditional and platform-based flows. In Versal ACAP, the recommended method for accessing DFX is to use block design containers (BDCs) on the IP integrator canvas. BDCs have a property that indicates whether the BDC is intended for use with DFX. If this property is set, the BDC becomes a reconfigurable partition (RP). Reconfigurable modules (RMs) can be added to the RP by associating additional block designs (BDs) with the BDC. Each BD represents a single RM. As with all DFX designs, determining the logical partition boundary and the correct design hierarchy is extremely important. After the BDCs are configured properly, the Vivado tools create the parent and child implementation runs to complete the compilation and generate the programming files.

Versal ACAP designs require special consideration if the NoC interconnect straddles a partition. To handle this situation, a NoC IP must be placed in the static portion of the design, and another instance of the NoC IP must be placed in the partition. Specialized interconnect called inter-NoC interconnect (INI) must be used to connect the two NoC IP. This ensures all RMs have a common set of physical interfaces but allows the RMs to have different addresses. Alternatively, you can use DFX Decoupler IP in the static region for PL-based crossings between the RM and the static region. However, Xilinx recommends using INI-based crossings at the static to RM boundary, because the NoC handles quiescing and shutdown of NoC paths internally and does not need manual intervention for decoupling.

The following figure shows the design hierarchy for a DFX design in which the static RM interface is based on a PL-based decoupler or a NoC-based INI.

Figure 1. DFX Design Hierarchy

DFX floorplans must be designed for the unique architecture of Versal ACAP, including NoC resources, hardened IP locations, and clocking resources. For more information, see the Vivado Design Suite User Guide: Dynamic Function eXchange (UG909) and the DFX Tutorial available from the Xilinx® GitHub repository.