When using the Versal ACAP traditional design flow, you must consider the following when planning your design:
- CIPS IP
- The Vivado tools generate the final programmable device image (PDI). To ensure the PDI is generated properly, CIPS IP must be placed in the design even if the processing system is not being used. The PMC is located in the CIPS and is required to boot the Versal device.
- Design Hierarchy and NoC Compiler
- One or more NoC IP can be instantiated in the Versal ACAP design as long as the IP are all located under a single BD hierarchy. This ensures that when the topmost BD is validated, the NoC compiler is called automatically and has complete visibility of all NoC master and slave units in the design, including their connectivity, bandwidth requirements, and relative priorities.
Note: If the design uses a BD top, the NoC Compiler always has visibility into all the NoC IP cores instantiated in the design.
- Simulation requires special connections to be created to the NoC to correctly model its connectivity. When the design is exported for simulation, an additional level of hierarchy is added to the design to represent the NoC connectivity. This process is transparent to you and is required for the NoC to simulate correctly.