The MBUFG primitive in Versal devices allows clock division at the leaf level to reduce clock track utilization and improve timing closure on synchronous CDCs. For DFX designs, MBUFG optimization is allowed only for static clock nets or internal RM clock nets. Boundary clock nets can continue to use BUFGCE_DIV/MMCM/PLL clocking primitives for clock division. However, this results in reduced QoR benefits compared to using MBUFG primitives, because MBUFGs provide common clock nodes closer to loads at the leaf level. Therefore, Xilinx recommends using MMCM/PLL clocking primitives inside partitions in the DFX design to convert boundary clock nets to internal clock nets, which can leverage the MBUFG optimizations provided by the Vivado tools. Special handling is required to ensure that BUFDIV_LEAF dividers are reset to their startup state during partial PDI download. For information on resetting BUFDIV_LEAF buffers, see Clock Primitives.