MBUFG Primitives - 2022.1 English

Versal ACAP Hardware, IP, and Platform Development Methodology Guide (UG1387)

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2022.1 English
The Versal architecture introduces a new clocking primitive called the MBUFG. The MBUFG receives an input clock and can provide multiple output clocks that are divisions or multiples of the input clock. Following are the MBUFG cell types:
for general global clocking
for general global clocking with division features similar to BUFGCE_DIV
for general global clocking with control features similar to BUFGCTRL
for global clocking with gigabit transceivers (GTs)
for global clocking generated by Control, Interface, and Processing System (CIPS) IP

The MBUFG cells instruct the implementation tools to use a single global clock routing track and leaf clock dividers and multipliers to recreate the output clocks. This reduces skew and greatly aids in timing closure for synchronous CDCs. The following figure shows a simple example in which a single clock input is connected to the input of the MBUFGCE to generate a clock and a divide-by-2 clock.

Figure 1. Recommended Topology for Versal ACAP Synchronous CDCs