When working with the Vitis environment, PL functionality is divided between the subsystem and the platform. Essential infrastructure IP (like CIPS, NoC, and external I/O controllers) must be included in the platform. However, you can choose where to include other PL blocks. In general, Xilinx strongly recommends including in the subsystem all of the blocks and IP involved in the processing chain of the system. This approach greatly increases the modularity of the design and enables more automation features. This increased flexibility is very important when developing, debugging, and optimizing tightly coupled PL and AI Engine blocks. For more information, see the this link in the Vitis Unified Software Platform Documentation: Application Acceleration Development (UG1393).