Netlist-Based I/O Planning - 2022.1 English

Versal ACAP Hardware, IP, and Platform Development Methodology Guide (UG1387)

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2022.1 English

Xilinx recommends assigning I/Os and clock logic constraints after the design has been synthesized. For Versal devices, Xilinx recommends instantiating all IP and I/Os along with basic logic in an RTL project. The project can then be synthesized. For designs using GT blocks, such as MRMAC or DCMAC, the Hard Block Planner provides a visual help to assign the GT Quad and the GT reference clock to valid sites and package pins. For Xilinx IP, such as memory interfaces and high-speed I/O interfaces, the Advanced IO Wizard allows for correct-by-construction pinout assignment. For legacy, low-performance interfaces using I/O logic, pinout can be performed using drag-and-drop onto the Package window.