When assigning logic to Pblocks with Versal ACAP SSI technology devices, you might need to perform NoC design planning to achieve optimal and consistent results throughout your design process. When performing NoC design planning, consider the following:
- When using SLR-level Pblocks in the implementation tools, consider constraining the NoC NMU/NSU in the Vivado IP integrator to match the implementation results.
- For NoC paths that begin or end at the DDRMC or PS, consider placing these paths in SLR0 to minimize latency.
- For NoC paths that do not begin or end at the DDRMC or PS, consider completely constraining these paths within SLRs (other than SLR0).
- Instead of pipelining across multiple SLRs using the AXI register slice, consider using the NoC.
In the following example, the PL-NoC paths highlighted in purple interface with the DDRMC and are constrained to SLR0 in the IP integrator. The NoC paths highlighted in pink are PL-NoC paths that are constrained to SLR1 in the IP integrator.
Figure 1. SLR-Level Design Planning in IP Integrator
